China Development Financial Holding has been granted a patent for a packet sorting and reassembly circuit module. This module includes components such as a header parser, information processing circuit, state tracking circuits, and an output arbiter, designed to analyze and reassemble TCP network packet segments efficiently. GlobalData’s report on China Development Financial Holding gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on China Development Financial Holding, was a key innovation area identified from patents. China Development Financial Holding's grant share as of June 2024 was 75%. Grant share is based on the ratio of number of grants to total number of patents.
Packet sorting and reassembly circuit module for tcp packets
The patent US11979479B1 describes a packet sorting and reassembly circuit module designed to enhance the processing of network packets transmitted via the Transmission Control Protocol (TCP). The module includes several key components: a header parser that analyzes packet segments to extract header information, an information processing circuit that transmits these segments along with sideband information to a state tracking and reassembly circuit, and an output arbiter that organizes and outputs the sorted packet segments. The information processing circuit is further detailed with subcomponents such as an information integration circuit, a payload calculation circuit, and a distributor, which work together to manage the packet data payload and facilitate the sorting process.
Additionally, the claims outline the functionality of the state tracking and reassembly circuit, which temporarily stores and reassembles packet segments based on the sideband information. The module also incorporates a connection comparison circuit to evaluate connection settings and determine the appropriate path for packet transmission. The output arbiter is structured with multiple queues to manage the output of both reassembled and directly transmitted packet segments. Notably, the circuit can identify retransmission packets and generate corresponding identification signals. The entire system is designed to operate based on the AXI4-Stream protocol, indicating its applicability in high-performance data processing environments.
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