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Adjusting cpu clock frequency based on input polling results

Source: United States Patent and Trademark Office(USPTO). Credit: Nasdaq Inc

A recently filed patent (Publication Number: US20230153256A1) describes an apparatus and method for optimizing the operation of processing circuitry in a computer system. The apparatus includes processing circuitry associated with an input/output (I/O) range and control circuitry. The processing circuitry is configured to deliver input data to an application and operates at a first clock frequency. The control circuitry instructs the processing circuitry to poll the I/O range for input data. The processing circuitry determines whether the polling results in the detection of input data at the I/O range. If a number of polls result in detection of input data, the processing circuitry operates at a second clock frequency that is higher than the first clock frequency.

The I/O range in the apparatus includes a set of memory addresses, with each address corresponding to a section of memory. The polling involves detecting read or write operations associated with an address in the set of memory addresses. The I/O range can consist of a single I/O port or multiple I/O ports.

The first part of the processing circuitry operates at a lower clock frequency to reduce energy consumption. If the number of polls does not result in the detection of input data, the processing circuitry operates in an energy-efficient mode at the first clock frequency. The control circuitry monitors the polling results and adjusts the clock frequency of the processing circuitry accordingly.

The method described in the patent involves operating the processing circuitry at a first clock frequency and polling the I/O range for input data. The processing circuitry determines whether the polling results in the detection of input data. If a number of polls result in detection of input data, the processing circuitry operates at a second clock frequency that is higher than the first clock frequency.

The computer-readable storage medium stores program instructions that, when executed by a processing system, cause the processing system to perform the method described above. The method includes operating the processing circuitry at a lower clock frequency to reduce energy consumption. If the number of polls does not result in the detection of input data, the processing circuitry operates in an energy-efficient mode at the first clock frequency. The control circuitry monitors the polling results and adjusts the clock frequency of the processing circuitry based on the results.

Overall, this patent describes a system and method for optimizing the operation of processing circuitry in a computer system by dynamically adjusting the clock frequency based on the detection of input data in the I/O range. This approach aims to improve performance while minimizing energy consumption.

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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.